Thin film transistor array substrate for a liquid crystal display

ABSTRACT

A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area. The passivation layer and the underlying layers are etched through the photoresist pattern to form a semiconductor pattern and contact windows. A pixel electrode, a supplemental gate pad and a supplemental data pad are then formed of indium tin oxide or indium zinc oxide. The gate and data line assemblies may be formed with a single layered structure. A black matrix and a color filter may be formed at the structured substrate before forming the pixel electrode, and an opening portion may be formed between the pixel electrode and the data line to prevent possible short circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation reissue application of co-pending U.S. Reissueapplication Ser. No. 10/749,153 filed on Dec. 31, 2003, now U.S. Pat.No. RE40,162 based upon U.S. Pat. No. 6,380,559, issued on Apr. 30,2002, which claims priority to Korean Patent Application Nos. 99-20515filed on Jun. 3, 1999, 99-27140 filed on Jul. 6, 1999, 99-27548 filed onJul. 8, 1999 and 99-29796 filed on Jul. 22, 1999, the disclosures ofwhich are incorporated by reference herein in their entirety.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor array (TFT)substrate for a liquid crystal display and a method for fabricating thesame, and more particularly, to a method for fabricating a TFT arraysubstrate of good performance in processing steps.

(b) Description of the Related Art

Generally, a liquid crystal display (LCD) is formed with two glasssubstrates, and a liquid crystal layer sandwiched between thesubstrates.

One of the substrates has a common electrode, a color filter and a blackmatrix, and the other substrate has pixel electrodes and thin filmtransistors (TFTs). The former substrate is usually called the “colorfilter substrate,” and the latter substrate is usually called the “TFTarray substrate.”

The TFT array substrate is fabricated by forming a plurality of thinfilms on a glass substrate, and performing photolithography with respectto the thin films. In photolithography, many masks should be used foruniformly etching the thin films, and this involves complicatedprocessing steps and increased production cost. Therefore, the number ofmasks becomes a critical factor in the fabrication efficiency of the TFTarray substrate.

Furthermore, contact windows tend to be over-etched during the TFTformation, causing contact failure. Thus, it is required that stable andrigid contact between the desired electrodes should be ensured in thedevice fabrication.

On the other hand, the black matrix provided at the color filtersubstrate should be formed with a certain width considering thealignment margin for the color filter substrate joining the TFT arraysubstrate. However, the larger black matrix reduces the aperture ratio.Therefore, the opening ratio of the black matrix should be alsoconsidered in fabricating the TFT array substrate.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a TFT arraysubstrate for a liquid crystal display of good performance, and a methodfor fabricating the same with a reduced number of masks.

It is another object of the present invention to provide a method forfabricating a TFT array substrate that ensures suitable contacts betweenthe electrode components.

It is still another object of the present invention to provide a methodfor fabricating a TFT array substrate with a suitable opening ratio.

These and other objects may be achieved by a TFT array substrateincluding a gate line assembly with gate lines proceeding in thehorizontal direction, gate electrodes branched from the gate lines, andgate pads connected to end portions of the gate lines to receivescanning signals from the outside and transmit them to the gate lines.The gate line assembly may be formed with a single, double or triplelayered structure. When the gate line assembly is formed with a doubleor triple layered structure, one layer is formed with a low resistancematerial while the other layer is formed with a material having goodcontact characteristics.

The gate line assembly is overlaid sequentially with a gate insulatinglayer, semiconductor patterns, and ohmic contact patterns.

A data line assembly is formed on the ohmic contact patterns with datalines proceeding in the vertical direction, data pads connected to endportions of the data lines to receive picture signals from the outside,and source electrodes branched from the data lines. The data lineassembly further includes drain electrodes for the TFTs, and conductivepatterns for the storage capacitors. The drain electrode is positionedopposite to the source electrode With respect to the gate electrodewhile being separated from the source electrode. The conductive patternis positioned above the gate line while overlapping the same. Theconductive pattern is connected to a pixel electrode to form a storagecapacitor. However, in case the overlapping of the pixel electrode andthe gate line can give a sufficient amount of storage capacity, theconductive pattern may be omitted. The data line assembly may have asingle, double or triple layered structure.

The semiconductor patterns have a shape similar to that of the data lineassembly and the underlying ohmic contact patterns. The semiconductorlayer extends to the peripheral portion of the substrate while coveringthe latter.

A passivation layer covers the data line, the data pad, the sourceelectrode, the drain electrode, the semiconductor pattern, and theoverlapping portions between the gate line and the data line.

Contact windows are formed at the passivation layer while exposing thedrain electrode and the data pad. The contact window exposing the drainelectrode may be extended toward the pixel area such that it can exposethe borderline of the drain electrode completely. Another contact windowis formed at the passivation layer while passing through thesemiconductor pattern and the gate insulating layer to expose the gatepad to the outside.

The pixel electrode is formed on the gate insulating layer at the pixelarea defined by the neighboring gate and data lines. The pixel electrodeis electro-physically connected to the drain electrode through thecontact window such that it receives picture signals from the TFT whilemaking the required electrical field in association with a commonelectrode. The pixel electrode is extended over the conductive pattern,and electro-physically connected to the latter such that it serves as astorage capacitor together with the conductive pattern and the gateline.

A subsidiary gate pad and a subsidiary data pad are formed on the gatepad and the data pad, respectively. The subsidiary gate and data padsare formed together with the pixel electrode with the same material, andcontact the gate and data pads, respectively.

An opening portion may be formed between the pixel electrode and thedata line to prevent a possible short circuit thereof.

According to one aspect of the present invention, the steps offabricating the TFT array substrate may be performed as follows.

A gate line assembly is first formed on a substrate by using a firstmask. Then a gate insulating layer, a semiconductor layer, a contactlayer, and first and second metal data line layers are deposited ontothe substrate with the gate line assembly in a sequential manner. A dataline assembly with a predetermined pattern is formed through etching thefirst and second metal data line layers by using a second mask. Thecontact layer is etched through the pattern of the data line assemblysuch that the contact layer has the same pattern as the data lineassembly.

A passivation layer is then deposited onto the structured substrate suchthat the passivation layer covers the semiconductor layer and the dataline assembly. A photoresist film is coated onto the passivation layer,and exposed to light by using a third mask. The photoresist film is thendeveloped to thereby form a photoresist pattern partially differentiatedin thickness.

A semiconductor pattern is formed by etching the passivation layer andthe underlying semiconductor layer at the pixel area through thephotoresist pattern. First and second contact windows are formed byetching the passivation layer and the underlying second layers of thedrain electrode and the data pad. The third contact window is formed byetching the passivation layer and the underlying semiconductor layer andgate insulating layer, and the second layer of the gate pad.

After the photoresist pattern is removed, a pixel electrode is formed byusing a fourth mask such that the pixel electrode is connected to thedrain electrode through the first contact window.

The second metal gate or data line layer may be formed with aluminum oraluminum alloy, and the first layer with chrome, molybdenum, ormolybdenum alloy. Subsidiary gate and data pads may be formed during thestep of forming the pixel electrode such that they are connected to thefirst layers of the gate and data pads through the second and thirdcontact windows. The pixel electrode as well as the subsidiary gate anddata pads may be formed with indium tin oxide or indium zinc oxide.

The etching with respect to the second layers of the drain electrode,the gate pad and the data pad may be performed by using a wet-etchingtechnique or a dry-etching technique.

The step of exposing the passivation layer positioned over the drainelectrode and at the pixel area may be performed by removing thephotoresist film over the passivation layer through oxygen-based ashing.

The third mask for forming the photoresist pattern may be provided witha transparent substrate, a first layer formed on the transparentsubstrate, and a second layer formed on the transparent substrate whileoverlapping with the first layer. The first layer has a lighttransmissivity lower than the transparent substrate, and the secondlayer has a light transmissivity different from those of the substrateand the first layer. The transparent substrate is established to have afirst portion without the first and second layers, a second portion withonly the first layer, and a third portion with both the first and secondlayers.

The transparent substrate has a light transmissivity of 90%, the firstlayer has a light transmissivity of 20-40%, and the second layer has alight transmissivity of 3% or less. The first and second layers may havea light transmissivity control pattern of slits or mosaics.

According to another aspect of the present invention, a black matrix anda color filter are formed on the structured substrate before the step offorming the pixel electrode.

After the semiconductor layer is etched to form a semiconductor patternand the remaining photoresist film is removed, an organic black matrixlayer is deposited onto the substrate, and etched through a fourth maskto thereby form a black matrix pattern. Alternatively, a blackphotoresist film may be used to form such a black matrix pattern.

A color filter is formed at the pixel area between the neighboring datalines, and at that point the formation of the pixel electrode andsubsidiary gate and data pads is complete.

According to still another aspect of the present invention, theformation of the passivation layer is deferred after the formation ofthe semiconductor pattern.

A gate line assembly is first formed at the substrate by using a firstmask. A gate insulating layer, a semiconductor layer, an ohmic contactlayer, and a metal data line layer are then sequentially deposited ontothe substrate. The metal data line layer, the ohmic contact layer andthe semiconductor layer are etched through a second mask to thereby formthe desired patterns with similar outlines except that the semiconductorpattern is present at the channel region between the source and drainelectrodes.

A passivation layer is deposited onto the substrate 10 with the dataline assembly, and etched through a third mask to thereby form contactwindows. An organic black matrix layer is then deposited onto thesubstrate, and etched through a fourth mask to thereby form a blackmatrix pattern. Thereafter, a color filter is formed, and the formationof a pixel electrode and subsidiary gate and data pads is complete.

In the above process, the black matrix pattern may perform the functionof the passivation layer without forming the latter. Furthermore, it isalso possible that the color filter is placed directly over thesubstrate and the gate line by removing the portion of the gateinsulating layer positioned between the neighboring data lines.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view illustrating a precursor substrate forfabricating a TFT array substrate according to a first preferredembodiment of the present invention where unit regions for the TFT arraysubstrate are indicated.

FIG. 2 is a schematic view illustrating the TFT array substrate withcircuit and line components according to the first preferred embodimentof the present invention.

FIG. 3 is an amplified view of the TFT array substrate shown in FIG. 2at one pixel area.

FIGS. 4 and 5 are cross sectional views of the TFT array substrate shownin FIG. 3 taken along the IV-IV′ line and the V-V′ line, respectively.

FIG. 6A is a plan view of the TFT array substrate shown in FIG. 3illustrating the step of forming a gate line assembly.

FIGS. 6B and 6C are cross sectional views of the TFT array substratetaken along the IVb-IVb′ line and the IVc-IVc′ line of FIG. 6A,respectively.

FIG. 7A is a plan view of the TFT array substrate shown in FIG. 3illustrating the step of forming a data line assembly.

FIGS. 7B and 7C are cross sectional views of the TFT array substratetaken along the VIIb-VIIb′ line and the VIIc-VIIc′ line of FIG. 7A,respectively.

FIG. 8A is a plan view of the TFT array substrate shown in FIG. 3illustrating the step of forming a semiconductor pattern and contactwindows.

FIGS. 8B and 8C are cross sectional views of the TFT array substratetaken along the VIIIb-VIIIb′ line and the VIIIc-VIIIc′ line of FIG. 8A,respectively.

FIGS. 9A and 9B are cross sectional views of the TFT array substratetaken along the VIIIb-VIIIb′ line and the VIIIc-VIIIc′ line of FIG. 8Aillustrating the step of exposing a photoresist film to light.

FIGS. 10A to 12 are cross sectional views of a mask for light-exposingthe photoresist film shown in FIGS. 9A and 9B.

FIGS. 13A and 13B are cross sectional views of the TFT array substratetaken along the VIIIb-VIIIb′ line and the VIIIc-VIIIc′ line of FIG. 8Aillustrating the step of developing the photoresist film.

FIGS. 14A and 14B are cross sectional views of the TFT array substratetaken along the VIIIb-VIIIb′ line and the VIIIc-VIIIc′ line of FIG. 8Aillustrating the step of etching some portions of a passivation layer.

FIGS. 15A and 15B are cross sectional views of the TFT array substratetaken along the VIIIb-VIIIb′ line and the VIIIc-VIIIc′ line of FIG. 8Aillustrating the step of ashing the etched portions of the passivationlayer.

FIGS. 16A and 16B are cross sectional views of the TFT array substratetaken along the VIIIb-VIIIb′ line and the VIIIc-VIIIc′ line of FIG. 8Aillustrating the step of etching other portions of the passivationlayer.

FIGS. 17A and 17B are cross sectional views of the TFT array substratetaken along the VIIIb-VIIIb′ line and the VIIIc-VIIIc′ line of FIG. 8Aillustrating the step of forming a semiconductor pattern.

FIGS. 18 to 23 are cross sectional views illustrating the steps offabricating a TFT array substrate in a sequential manner according to asecond preferred embodiment of the present invention.

FIGS. 24 to 29 are cross sectional views illustrating the steps offabricating a TFT array substrate in a sequential manner according to athird preferred embodiment of the present invention.

FIG. 30A is a plan view of a TFT array substrate according to a fourthpreferred embodiment of the present invention.

FIGS. 30B and 30C are cross sectional views of the TFT array substratetaken along the III-III′ line and the IV-IV′ line of FIG. 30Aillustrating the step of exposing a photoresist film to light.

FIG. 31 is a cross sectional view of a mask for light-exposing thephotoresist film shown in FIGS. 30B and 30C.

FIGS. 32A and 32B are cross sectional views of the TFT array substratetaken along the III-III′ line and the IV-IV′ line of FIG. 30Aillustrating the step of developing the photoresist film.

FIGS. 33A and 33B are cross sectional views of the TFT array substratetaken along the line and the IV-IV′ line of FIG. 30A illustrating thestep of etching some portions of a passivation layer.

FIGS. 34A and 34B are cross sectional views of the TFT array substratetaken along the line and the IV-IV′ line of FIG. 30A illustrating thestep of ashing the etched portions of the passivation layer.

FIGS. 35A and 35B are cross sectional views of the TFT array substratetaken along the line III-III′ line and the IV-IV′ line of FIG. 30Aillustrating the step of etching other portions of the passivationlayer.

FIGS. 36A and 36B are cross sectional views of the TFT array substratetaken along the III-III′ line and the IV-IV′ line of FIG. 30Aillustrating the step of forming a semiconductor pattern.

FIGS. 37A and 37B are cross sectional views of the TFT array substratetaken along the III-III′ line and the IV-IV′ line of FIG. 30Aillustrating the step of forming a pixel electrode.

FIG. 38A is a plan view of a TFT array substrate according to a fifthpreferred embodiment of the present invention.

FIG. 38B is a cross sectional view of the TFT array substrate takenalong the II-II′ line of FIG. 38A illustrating the step of forming ablack matrix pattern.

FIG. 39 is a cross sectional view of the TFT array substrate taken alongthe II-II′ line of FIG. 38A illustrating the step of forming a colorfilter.

FIG. 40 is a cross sectional view of the TFT array substrate taken alongthe II-II′ line of FIG. 38A illustrating the step of forming a pixelelectrode.

FIG. 41A is a plan view of a TFT array substrate according to a sixthpreferred embodiment of the present invention.

FIG. 41B is a cross sectional view of the TFT array substrate takenalong the IX-IX′ line of FIG. 41A.

FIG. 42A is a plan view of a TFT array substrate according to a seventhpreferred embodiment of the present invention.

FIG. 42B is a cross sectional view of the TFT array substrate takenalong the XI-XI′ line of FIG. 42A illustrating the step of forming asemiconductor pattern.

FIG. 43 is a cross sectional view of the TFT array substrate taken alongthe XI-XI′ line of FIG. 42A specifically illustrating the step offorming the semiconductor pattern.

FIG. 44 is a cross sectional view of the TFT array substrate taken alongthe XI-XI′ line of FIG. 42A illustrating the step of forming a blackmatrix pattern.

FIG. 45 is a cross sectional view of the TFT array substrate taken alongthe XI-XI′ line of FIG. 42A illustrating the step of forming a colorfilter and a pixel electrode.

FIG. 46A is a plan view of a TFT array substrate according to an eighthpreferred embodiment of the present invention.

FIG. 46B is a cross sectional view of the TFT array substrate takenalong the XVI-XVI′ line of FIG. 46A.

FIG. 47A is a plan view of a TFT array substrate according to a ninthpreferred embodiment of the present invention.

FIG. 47B is a cross sectional view of the TFT array substrate takenalong the XVI-XVI′ line of FIG. 47A.

FIG. 48A is a plan view of a TFT array substrate according to a tenthpreferred embodiment of the present invention.

FIG. 48B is a cross sectional view of the TFT array substrate takenalong the XXI-XXI′ line of FIG. 48A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of this invention will be explained with referenceto the accompanying drawings.

First Preferred Embodiment

FIGS. 1 to 5 illustrate a TFT array substrate according to a firstpreferred embodiment of the present invention.

A plurality of panel regions for LCDs may be made at one insulatingsubstrate at the same time. For example, as shown in FIG. 1, four panelregions 110, 120, 130 and 140 are made with display areas 111, 121, 131and 141, and peripheral areas 112, 122, 132 and 142. TFTs, lines andpixel electrodes for the main components are repeatedly arranged at thedisplay areas 111 to 141, whereas pads and other static electricityprotection circuits for the components connected to the driving circuitsare provided at the peripheral areas 112 to 142.

The display areas 111 to 141 and the peripheral areas 112 to 142 aredivided into several regions, and each region is light-exposed by astepper. A photoresist film coated the substrate is exposed to lightusing identical or different masks per region. After the exposure, thephotoresist film is wholly developed to form a photoresist pattern, andthe underlying thin films are etched through the photoresist pattern toform thin film patterns. Such thin film patterns are repeated to formthe TFT array substrate.

FIG. 2 is a schematic view outlining the TFT array substrate shown inFIG. 1 at one panel region where the display area is indicated by thelong and short dashed line.

As shown in FIG. 2, a plurality of TFTs 3, pixel electrodes 82, gatelines 22 and data lines 62 electrically connected to the TFTs 3 areprovided at the display area. Gate pads 24 placed at the end portions ofthe gate lines 22, and data pads 64 at the end portions of the datalines 62 are provided at the peripheral area. A gate line shorting bar 4and a data line shorting bar 5 are further provided at the peripheralarea to equipotentially interconnect the gate lines 22 and the datalines 62. neighboring gate and data line shorting bars 4 and 5 areelectrically connected to each other via a shorting bar connectionmember 6. Completing the device fabrication, the shorting bars 4 and 5are cut away along the dotted line 2. Contact windows 7 interconnect theshorting bar connection member 6 and the neighboring shorting bars 4 and5.

FIG. 3 is an amplified view of the TFT array substrate shown in FIG. 2at one pixel area, and FIGS. 4 and 5 are cross sectional view takenalong the IV-IV′ and V-V′ lines, respectively.

First, a gate line assembly is formed on the insulating substrate 10.The gate line assembly includes gate lines 22 proceeding in thehorizontal direction, gate electrodes 26 branched from the gate lines22, and gate pads 24 connected to end portions of the gate lines 22 toreceive scanning signals from the outside and transmit them to the gatelines 22.

The gate line assembly may be formed with a single, double or triplelayered structure. When the gate line assembly is formed with a doubleor triple layered structure, one layer is preferably formed of a lowresistance material and the other layer of a material having a goodcontact characteristic.

In this preferred embodiment, a gate line assembly with a double layeredstructure will be introduced. That is, the gate line assembly includeslower layers 221, 241 and 261, and upper layers 222, 242 and 262. Thelower layers 221 to 261 are formed with a metallic material such as Cr,Mo, or Mo alloy that exhibits a good contact characteristic with respectto indium tin oxide (ITO) or indium zinc oxide (IZO). In contrast, theupper layers 222 to 262 are formed with a low resistance metallicmaterial such as Al or Al alloy.

The gate line assembly is overlaid sequentially with a gate insulatinglayer 30, semiconductor patterns 42 and 48, and ohmic contact patterns55, 56 and 58. The gate insulating layer 30 is formed with siliconnitride (SiN_(x)). The semiconductor patterns 42 and 48 are formed ofhydrogenated amorphous silicon. The ohmic contact patterns 55, 56 and 58are formed with amorphous silicon doped with n-type impurities such asphosphorus (P).

A data line assembly is formed on the ohmic contact patterns 55, 56 and58. The data line assembly includes data lines 62 proceeding in thevertical direction, data pads 64 connected to end portions of the datalines 62 to receive picture signals from the outside, and sourceelectrodes 65 branched from the data lines 62. The data line assemblyfurther includes drain electrodes 66 for the TFTs, and conductivepatterns 68 for the storage capacitors. The drain electrode 66 ispositioned opposite to the source electrode 65 with respect to the gateelectrode 26 and separated from the source electrode 65. The conductivepattern 68 is positioned above the gate line 22 while overlapping thesame. The conductive pattern 68 is connected to a pixel electrode 82 toform a storage capacitor. However, if the pixel electrode 82 and thegate line 22 can generate sufficient storage capacity, the conductivepattern 68 may be omitted.

In the following description, it is assumed that the conductive pattern68 for the storage capacitor is present.

The data line assembly may have a single, double or triple layeredstructure. In this preferred embodiment, the double layered structure isused for the data line assembly. That is, the data line assemblyincludes lower layers 621, 641, 651, 661 and 681, and upper layers 622,642, 652 and 662. The lower layers 621 to 681 are formed of a metallicmaterial such as Cr, Mo or Mo alloy that exhibits a good contactcharacteristic with respect to ITO or IZO. The upper layers 622 to 662are formed of a low resistance metallic material such as Al or Al alloy.As shown in FIG. 5, among the components of the data line assembly, onlythe conductive pattern 68 has a single layered structure with the lowerlayer 681.

The ohmic contact patterns 55, 56 and 58 reduce the contact resistancebetween the semiconductor patterns 42 and 48 and the data line assembly,and have the same shape as that of the data line assembly.

The semiconductor patterns 42 and 48 have a shape similar to that of thedata line assembly and the underlying ohmic contact patterns 55, 56 and58. Specifically, the semiconductor pattern 48 for the storage capacitorhas the same shape as that of the conductive pattern 68 and theunderlying ohmic contact pattern 58, while the shape of thesemiconductor pattern 42 for the TFT differs from that of the data lineassembly and the underlying ohmic contact patterns 55 and 56. That is,the source electrode 65 is separated from the drain electrode 66 at thechannel region of the TFT, and the ohmic contact pattern 55 under thesource electrode 65 is also separated from the ohmic contact pattern 56under the drain electrode 66. In contrast, the semiconductor pattern 42continuously proceeds at the channel region of the TFT. Thesemiconductor layer extends to the peripheral portion of the substrate10 while covering the latter.

A passivation layer 70 covers the data line 62, the data pad 64, thesource electrode 65, the drain electrode 66, the semiconductor pattern42, and the overlapping portions between the gate line 22 and the dataline 62.

Contact windows 71 and 73 are formed at the passivation layer 70 whileexposing the drain electrode 66 and the data pad 64. The contact window71 exposing the drain electrode 66 may be extended toward the pixel areasuch that it can expose the borderline of the drain electrode 66completely. The Al-based upper layers 642 and 662 of the data pad 64 andthe drain electrode 66 are removed such that the Cr-based lower layers641 and 661 thereof are exposed through the contact windows 71 and 73.Another contact window 72 is formed at the passivation layer 70 whilepassing through the semiconductor pattern 42 and the gate insulatinglayer 30 to expose the gate pad 24 to the outside. The upper layer 242of the gate pad 24 is removed such that the lower layer 241 thereof isexposed through the contact window 72.

The passivation layer 70 may be formed of an organic insulating materialsuch as silicon nitride and acryl-based materials. The passivation layer70 protects the channel portion of the semiconductor pattern 42 betweenthe source and drain electrodes 65 and 66.

The aforementioned pixel electrode 82 is formed on the gate insulatinglayer 30 at the pixel area enclosed by the neighboring gate and datalines 22 and 62. The pixel electrode 82 is electro-physically connectedto the underlayer 661 of the drain electrode 66 through the contactwindow 71 such that it receives picture signals from the TFT whilemaking the required electrical field in association with a commonelectrode. The pixel electrode 82 is formed of a transparent conductivematerial such as ITO or IZO. The pixel electrode 82 is extended over theconductive pattern 68, and electro-physically connected to the lattersuch that it serves as a storage capacitor together with the conductivepattern 68 and the gate line 22.

In the meantime, a supplemental gate pad 84 and a supplemental data pad86 are formed on the gate pad 24 and the data pad 64, respectively. Thesupplemental gate and data pads 84 and 86 are formed together with thepixel electrode 82 with the same material, and contact the Cr-basedlower layers 241 and 641 of the gate and data pads 24 and 64,respectively. The supplemental gate and date pads 84 and 86 strengthenthe adhesion between the gate 24 and the data pad 64 and the externalcircuit devices and protect them. However they may be dispensed with.

The pixel electrode 82, the supplemental gate and data pads 84 and 86directly contact the Cr- or Mo-based lower layers 661, 841 and 861 ofthe drain electrode 66, and the gate and data pads 24 and 64, whichresults in stable and good contacts between them.

In a reflection-type liquid crystal display, an opaque conductivematerial may be used for the pixel electrode 82 instead of ITO or IZO.

A method for fabricating the TFT array substrate according to the firstpreferred embodiment will be now explained with reference to FIGS. 3 to5 and FIGS. 6A to 17B.

As shown in FIGS. 6A to 6C, a first metal gate line layer of chrome,molybdenum or molybdenum alloy is deposited onto a substrate 10 to athickness of 500-1,500 Å. A second metal gate line layer of aluminum oraluminum alloy is then deposited onto the first gate line layer to athickness of 1,000-4,000 Å. The first and second metal gate line layersare wet or dry-etched through a first mask so that a double-layered gateline assembly is formed at the substrate 10. The gate line assemblyincludes a gate line 22 with lower layer 221 and upper layer 222, a gatepad 24 with lower layer 241 and upper layer 242, and a gate electrode 26with lower layer 261 and upper layer 262.

Thereafter, as shown in FIGS. 7A to 7C, a gate insulating layer 30having a thickness of 1,500-5,000 Å, a semiconductor layer 40 having athickness of 500-1,500 Å, and an ohmic contact layer 50 having athickness of 300-600 Å are sequentially deposited onto the substrate 10along with the gate line assembly through chemical vapor deposition. Thegate insulating layer 30 is formed of silicon nitride, the semiconductorlayer 40 of amorphous silicon (a-Si), and the ohmic contact layer 50 ofdoped amorphous silicon (n⁺a-Si).

A first metal data line layer of chrome, molybdenum or molybdenum alloyis then deposited onto the ohmic contact layer 50 to a thickness of500-1,500 Å. A second metal data line layer of aluminum or aluminumalloy is deposited onto the first data line layer to a thickness of500-4,000 Å. The first and second data line layers are etched through asecond mask together with the underlying ohmic contact layer 50 to forma double-layered data line assembly. The data line assembly includes adata line 62 with lower layer 621 and upper layer 622, a data pad 64with lower layer 641 and upper layer 642, a source electrode 65 withlower layer 651 and upper layer 652, a drain electrode 66 with lowerlayer 661 and upper layer 662, and a conductive pattern 68 with lowerlayer 681 and upper layer 682. At this time, the ohmic contact layer 50is also etched to form a first contact pattern 55 for the data line 62,the data pad 64 and the source electrode 65, a second contact pattern 56for the drain electrode 66, and a third contact pattern 58 for theconductive pattern 68. The conductive pattern 68 with the third contactpattern 58 may be omitted.

Thereafter, as shown in FIGS. 8A to 8C, a passivation layer 70 ofsilicon nitride is deposited onto the substrate 10 through chemicalvapor deposition to a thickness of 3,000 Å. The passivation layer 70 isthen etched through a third mask together with the underlyingsemiconductor layer 40 and gate insulating layer 30. As a result, thepassivation layer 70 and the upper layer 662 are removed from the drainelectrode 66 to form a first contact window 71. The passivation layer70, the semiconductor layer 40, the gate insulating layer 30 and theupper layer 242 are removed from the gate pad 24 to form a secondcontact window 72. The passivation layer 70 and the upper layer 642 areremoved from the data pad 64 to form a third contact window 73. Theupper layer 682 is removed from the conductive pattern 68. Furthermore,the passivation layer 70 and the semiconductor layer 40 at the pixelarea between the neighboring data lines 62 are removed to form thechannel region only at the required portion.

The etching process using the third mask will be now described indetail.

A photoresist film PR having a thickness of 5,000-30,000 Å is coatedonto the passivation layer 70, and exposed to light through the thirdmask. As shown in FIGS. 9A and 9B, the light exposure at the displayarea D is different from the light exposure at the peripheral area P.That is, the exposed portion C of the photoresist film PR at the displayarea D reacts to the light such that the molecules thereof are partiallyresolved to a predetermined depth from the surface while leaving themolecules thereunder unresolved. In contrast, the exposed portion B ofthe photoresist film PR at the peripheral area P reacts to the lightsuch that the molecules thereof are completely resolved to the bottom.

In order to perform such a differential light exposure, the lighttransmissivity of the third mask corresponding to the display area D andthe peripheral area P of the photoresist film PR should be controlledappropriately. Three types of techniques will be here introduced.

FIGS. 10A to 12 illustrate possible structures of the third mask foretching the passivation layer 70 along with the underlying layers.

First, separate masks can be used for the third mask to perform themasking operation with respect to the display area D and the peripheralarea P of the photoresist film PR, respectively.

As shown in FIGS. 10A and 10B, a mask 300 for the display area D and amask 400 for the peripheral area P are formed with substrates 310 and410, chrome-based opaque films 320 and 420 formed on the substrates 310and 410, and semitransparent pellicles 330 and 430 covering thesubstrates 310 and 410 with the opaque films 320 and 420. It ispreferable that the light transmissivity of the opaque films 320 and 420be 3% or less, the light transmissivity of the pellicle 430 of the mask400 for the peripheral area P to be 90% or more, and the pellicle 330 ofthe mask 300 for the display area D to be 20-40% that is in the range of20-60% of the light transmissivity of the pellicle 430 for theperipheral area P.

Meanwhile, patterns of slit or lattice with an opening width of about2.5 μm that is smaller than the resolution capability of the lightsource for exposure may be formed as a replacement for thesemitransparent pellicle 330 for the display area D.

Alternatively, as shown in FIGS. 11A and 11B, a chrome-based thin film350 with a thickness of 100-300 Å covers the entire surface of the mask300 for the display area D while being positioned under the opaque film320, whereas such a chrome-based thin film is absent at the mask 400 forthe peripheral area P. In this case, the pellicle 340 of the mask 300for the display area D may have the same light transmissivity as that ofthe pellicle 430 of the mask 400 for the peripheral area P.

Of course, the above two techniques may be used together in a suitableapplication.

The above two types of masks can be applied for use in partitionedexposure with a stepper, and separately perform the masking operationwith respect to the display area D and the peripheral area P. Thethickness of the target film can be also controlled by making the lightexposure period different depending on the display area D and theperipheral area P.

On the other hand, only one mask can be used for the light exposure withrespect to the display and the peripheral areas D and P at the same timewhile controlling the amount of light applied thereto. FIG. 12illustrates the structure of such a mask 500.

As shown in FIG. 12, a light transmissivity control film 550 is formedon a substrate 510 for the mask 500, and an opaque film 520 is formed onthe light transmissivity control film 550. Whereas the lighttransmissivity control film 550 for the display area D is formed on theentire surface of the substrate 510, the light transmissivity controlfilm 550 for the peripheral area P is formed only under the opaque film520. That is, two or more patterns with different thickness are formedon the substrate 510. Of course, such a light transmissivity controlfilm may be formed on the entire surface of the substrate 510 both atthe display and the peripheral areas D and P. In this case, the lighttransmissivity of the light transmissivity control film 550 for theperipheral area P should be established to be higher than that of thelight transmissivity control film 550 for the display area D.

In the fabrication process of the mask 500, a light transmissivitycontrol film 550, and an opaque film 520 with an etching ratio differentfrom that of the light transmissivity control film 550 are sequentiallydeposited onto the substrate 510. A photoresist film is coated on theentire surface of the substrate 510 with the light transmissivity film550 and the opaque film 520, exposed to light, and developed to form aphotoresist pattern. The opaque layer 520 is then etched by using thephotoresist pattern for the mask. The photoresist pattern is thenremoved, and a second photoresist pattern is formed while exposing theportions of the light transmissivity film 550 corresponding to thecontact windows at the peripheral area P to the outside. The lighttransmissivity film 550 is then etched by using the second photoresistpattern for a mask. A semitransparent pellicle 530 is finally formed onthe substrate 510 with the patterns of the light transmissivity film 550and the opaque layer 520.

Meanwhile, the portions of the photoresist film PR with the underlyingmetal gate or data line assembly may be applied with a larger amount oflight due to the light reflected against the metallic component.Therefore, in order to prevent such a problem, a new layer forintercepting the reflected light, for example a colored photoresist filmPR, may be introduced.

As shown in FIGS. 13A and 13B, when the photoresist film PR exposedthrough the third mask is developed, a photoresist pattern PR results.That is, some portions B of the photoresist film at the peripheral areaP over the gate and data pads 24 and 64 are completely removed, and someportions C of the photoresist film at the display area D over the drainelectrode 66 and the pixel area are partially removed with a resultingsmall thickness. The remaining portions of the photoresist film at thedisplay and the peripheral areas D and P are left with a relativelylarge thickness. In this process, as shown in FIG. 13B, the photoresistfilm having a small thickness may be formed over the conductive pattern68.

The thickness of the thin photoresist film is preferably in the range of350-10,000 Å that is one fourth to one seventh of the initial thickness,and more preferably in the range of 1,000-6,000 Å. For instance, theinitial thickness of the photoresist film may be established to be25,000-30,000 Å, and the thickness of the thin photoresist film to be3,000-5,000 Å by controlling the light transmissivity of the mask at thedisplay area D to 30%. However, since the resulting thickness isdetermined in accordance with the processing conditions, the pellicle ofthe mask, the thickness of the chrome-based film, and the lighttransmissivity of the light transmissivity control film, the exposingtime should be controlled depending upon such processing conditions.

Alternatively, such a thin photoresist film may be formed by using acommon processing technique including the steps of exposing anddeveloping the photoresist film, and then performing the followingoperation, whereby the photoresist pattern PR and the underlyingpassivation layer 70, semiconductor layer 40 and gate insulating layer30 are etched by using a dry etching technique, passivation

In the etching process, the A portion of the photoresist pattern PRshould be partially left, the passivation layer 70, semiconductor layer40 and gate insulating layer 30 positioned under the B portion of thephotoresist pattern PR should be removed, and the passivation layer 70and semiconductor layer 40 under the C portion of the photoresistpattern PR should be removed, while leaving the gate insulating layer30.

For this purpose, a dry etching technique that is capable of etching thephotoresist pattern PR and the underlying layers at the same time may beused.

Alternatively, in order to prevent only partial removal of thesemiconductor layer 40 over the gate insulating layer 30 due to thenon-uniform thickness of the resulting photoresist film, the photoresistpattern PR and the underlying layers can be etched through severaletching steps as described below.

As shown in FIGS. 14A and 14B, the passivation layer 70 at the B portionof the photoresist film over the data pad 64 is dry-etched whileexposing the data pad 64. The passivation layer and the underlyingsemiconductor layer 40 and gate insulating layer 30 at the B portion ofthe photoresist film over the gate pad 24 is dry-etched while partiallyleaving the gate insulating layer 30. At this time, the gate insulatinglayer 30 over the gate pad 24 may be completely removed while exposingthe underlying gate pad 24. SF₆+N₂ or SF₆+HCL can be used for the dryetching, and the photoresist film PR at the display area D may bepartially removed during the dry etching. Therefore, the consumption ofthe photoresist film PR should be controlled such that the passivationlayer 70 at the display area D is not exposed to the outside. In thisprocess, as shown in FIG. 14B, the thickness of the photoresist film PRover the conductive pattern 68 becomes reduced by as much as that of thephotoresist film PR at the display area D.

Thereafter, as shown in FIGS. 15A and 15B, the C portion of thephotoresist film PR over the passivation layer 70 are removed throughoxygen-based ashing. At this time, considering that the C portion of thephotoresist film PR may be left with a non-uniform thickness, the ashingshould be sufficiently performed by using N₆+O₂ or Ar+O₂. In this way,even though the C portion of the photoresist film is non-uniformlyformed with a small thickness, it can be completely removed.

Thereafter, as shown in FIGS. 16A and 16B, the passivation layer 70 overthe drain electrode 66, the pixel area and the conductive pattern 68 aswell as the gate insulating layer 30 over the gate pad 24 are removed byusing the photoresist pattern PR for a mask. In order to make etchingconditions suitable for the semiconductor layer 40 and the passivationlayer 70, the etching gas preferably contains large amount of O₂ or CF₄.SF₆+N₂, SF₆+O₂, CF₄+O₂ or CF₄+CHF₃+O₂ are preferably used for the dryetching.

As shown in FIGS. 17A and 17B, the semiconductor layer 40 between theneighboring data lines 62 is removed by etching, to complete thesemiconductor patterns 42 and 48. Cl₂+O₂ or SF₆+HCl+O₂+Ar is preferablyused for etching the semiconductor layer 40.

Thereafter, as shown in FIGS. 4 and 5, the upper layer 242 of the gatepad 24, the upper layer 662 of the drain electrode 66, the upper layer642 of the data pad 64, and the upper layer 682 of the conductivepattern 68 exposed to the outside are removed through dry-etching orwet-etching, and the remaining photoresist film PR is also removed. AnITO or IZO film is deposited onto the substrate 10, and etched through afourth mask. Consequently, a pixel electrode 82, a supplemental gate pad84 and a supplemental data pad 86 are formed while contacting the lowerlayer 661 of the drain electrode 66, the lower layer 241 of the gate pad24, and the lower layer 641 of the data pad 64, respectively.

As described above, in this preferred embodiment, the semiconductorpatterns 42 and 48 together with the contact windows 71 to 73 is formedthrough one masking process and the desired TFT array substrate can befabricated using only four masks. Furthermore, multiple etching can beuniformly performed on a large target area with different depth. Inaddition, the data or gate line assembly may have a double-layeredstructure with a low-resistance aluminum-based layer, eliminating poorcontact characteristics of an aluminum-based layer at the pad portions.

In the meantime, when the upper layer 662 of the drain electrode 66, andthe upper layer 642 of the data pad 64 are etched, over-etching isliable to occur inside of the edge of the passivation layer 70. In thiscase, the ITO or IZO film pattern for the pixel electrode 82 at theover-etched portion may be broken.

Second Preferred Embodiment

FIGS. 18 to 23 illustrate a method for fabricating a TFT array substrateaccording to a second preferred embodiment of the present invention. Inthis preferred embodiment, the processing steps are the same as thoserelated to the first preferred embodiment up to the step of depositingthe passivation layer 70 onto the substrate 10.

As shown in FIG. 18, a photoresist film PR is coated onto thepassivation layer 70. The photoresist film PR is exposed to lightthrough a third mask, and developed to form a photoresist pattern. Thatis, the portion B of the photoresist film PR over the gate pad 24, datapad 64 and drain electrode 66 is completely removed. The portion C ofthe photoresist film PR adjacent to the portion B over the drainelectrode 66 and the data pad 64 and positioning at the pixel area ispartially removed such that it has a small thickness. The remainingportion A of the photoresist film PR is left without being consumed.

Thereafter, as shown in FIG. 19, the passivation layer 70, thesemiconductor layer 40 and the gate insulating layer 30 at the B portionof the photoresist film PR are dry-etched such that the gate pad 24, thedrain electrode 66 and the data pad 64 are exposed to the outside.

In this process, the A portion of the photoresist film PR may bepartially removed.

Then, as shown in FIG. 20, the upper layer 242 of the gate pad 24, theupper layer 662 of the drain electrode 66 and the upper layer 642 of thedata pad 64 are dry or wet-etched such that the lower layers 241, 661and 641 are exposed. The thin photoresist film PR over the drainelectrode 66, the pixel area and the data pad 64 are removed throughoxygen-based ashing to expose the underlying passivation layer 70.

As shown in FIG. 21, the exposed passivation layer 70 over the drainelectrode 66 and the data pad 64 is dry-etched such that the upper layer662 of the drain electrode 66 and the upper layer 642 of the data pad 64are exposed to the outside through the contact windows 71 and 73. Atthis time, the passivation layer 70 at the pixel area and the underlyingsemiconductor layer 40 are also removed to complete semiconductorpatterns 42 and 48.

As shown in FIG. 22, the remaining photoresist film PR is removed tocomplete the contact windows 71, 72 and 73.

As shown in FIG. 23, an ITO or IZO film is deposited onto the entiresurface of the substrate 10, and etched through a fourth mask. As aresult, a subsidiary gate pad 84, a pixel electrode 82 and a subsidiarydata pad 86 are formed while contacting the lower layer 241 of the gatepad 24, the lower layer 661 of the drain electrode 66 and the lowerlayer 641 of the data pad 64, respectively.

As described above, in this preferred embodiment, the semiconductorpatterns 42 and 48 together with the contact windows 71 to 73 is formedthrough one masking process so that the desired TFT array substrate canbe fabricated using only four mask. Furthermore, multiple etching can beuniformly performed on large target areas with different depth. Inaddition, the data or gate line assembly may have a double-layeredstructure with a low-resistance aluminum-based layer, not showing poorcontact characteristics of an aluminum-based layer at the pad portions.

Furthermore, removing the passivation layer 70 after removing the upperlayer 662 of the drain electrode 66 and the upper layer 642 of the datapad 64 eliminates the problem of over-etching the upper layers 662 and642. Therefore, the pixel electrode 82 and the subsidiary data pad 86 atthe contact windows 71 and 73 can be prevented from breaking. Inaddition, the above structure can mitigate the height differences of thecomponents at the contact windows 71 to 73.

Third Preferred Embodiment

FIGS. 24 to 29 illustrate the steps of fabricating a TFT array substrateaccording to a third preferred embodiment of the present invention wherea photosensitive organic layer is used for the passivation layer. Inthis preferred embodiment, the processing steps are similar to thoserelated to the first preferred embodiment prior to the step ofdepositing a passivation layer onto the substrate 10.

As shown in FIG. 24, a photosensitive passivation layer 80 of aphotosensitive organic material is deposited onto the substrate 10 to athickness of 3,000 Å. The photosensitive passivation layer 80 is thenexposed to light through a third mask, and developed to form aphotoresist pattern. That is, the portion B of the photosensitivepassivation layer 80 over the gate pad 24, the data pad 64 and the drainelectrode 66 is completely removed. The portion C of the photosensitivepassivation layer 80 adjacent to the portion B over the drain electrode66 and the data pad 64 and positioned at the pixel area is partiallyremoved such that it has a small thickness. The remaining portion A ofthe photosensitive passivation layer 80 is left intact.

Thereafter, as shown in FIG. 25, passivation the semiconductor layer 40and the gate insulating layer 30 are dry-etched through the removedportion B of the photosensitive passivation layer 80 exposing the gatepad 24, the drain electrode 66 and the data pad 64.

Then, as shown in FIG. 26, the upper layer 242 of the gate pad 24, theupper layer 662 of the drain electrode 66 and the upper layer 642 of thedata pad 64 are dry or wet-etched exposing the lower layers 241, 661 and641.

As shown in FIG. 27, the thin photosensitive passivation layer 80remaining over the drain electrode 66 and the data pad 64 is removedthrough oxygen-based aching to expose the upper layer 662 of the drainelectrode 66 and the upper layer 642 of the data pad 64 to the outsidethrough the contact windows 71 and 73. At this time, the thinphotosensitive passivation layer 80 remaining at the pixel area is alsoremoved to expose the underlying semiconductor layer 40.

As shown in FIG. 28, the exposed semiconductor layer 40 is dry-etched tocomplete semiconductor patterns 42 and 48.

As shown in FIG. 29, an ITO or IZO film is deposited onto the entiresurface of the substrate 10, and etched through a fourth mask. As aresult, a supplemental gate pad 84, a pixel electrode 82 and asubsidiary data pad 86 are completed while contacting the lower layer241 of the gate pad 24, the lower layer 661 of the drain electrode 66and the lower layer 641 of the data pad 64, respectively.

This preferred embodiment, in addition to the advantages related to theprevious preferred embodiments, simplifies the processing steps becausethe separate steps of processing a photoresist film after the formationof the passivation layer are not necessary.

Fourth Preferred Embodiment

FIGS. 30A to 37B illustrate the steps of fabricating a TFT arraysubstrate according to a fourth preferred embodiment of the presentinvention. In this preferred embodiment, other components and structuresof the TFT array substrate are similar to those related to the firstpreferred embodiment except that a single layered structure is used forthe gate and data line assemblies, the conductive pattern 68 for thestorage capacitor is eliminated, and an opening portion 31 is formedbetween the pixel electrode 82 and the data line 62 while exposing thesubstrate 10. The gate and data line assemblies having a single layeredstructure of a metallic or conductive material such as Al, Al alloy, Mo,Mo—W alloy, Cr, and Ta are formed to a thickness of 1,000-4,000 Å. Theopening portion 31 is to prevent a short circuit between the pixelelectrode 82 and the data line 62 occurring when the semiconductorpattern 42 is over-extended toward the periphery of the data line 62,and connected to the data line 62.

In the method of fabricating the TFT array substrate according to thefourth preferred embodiment, the processing steps are similar as thoserelated to the first preferred embodiment up to the step of depositingthe passivation layer onto the substrate except that the gate and dataline assemblies are formed with a single layered structure.

As shown in FIG. 30B, a photoresist film PR is coated onto thepassivation layer 70. The photoresist film PR is exposed to lightthrough a third mask. The light exposure to the photoresist film PR atthe display area D is mainly different from that at the peripheral areaP. That is, the exposed portions C and E of the photoresist film PR atthe display area D over the drain electrode 66 and the pixel area reactto light such that the molecules thereof are partially resolved to apredetermined depth from the surface while leaving the moleculesthereunder intact. In contrast, the exposed portion B of the photoresistfilm PR at the peripheral area P over the gate pad 24 and the data pad64 reacts to the light such that the molecules thereof are completelyresolved to the bottom.

The exposed portion B of the photoresist film PR at the display area Dbetween the pixel area and the data line 62 also reacts to the lightsuch that the molecules thereof are completely resolved to the bottom.

In order to achieve such different light exposures, the lighttransmission of the third mask at the display area D and the peripheralarea P should be controlled appropriately.

As shown in FIG. 31, the third mask for the above etching is formed witha transparent substrate 610. The transparent substrate 610 issequentially overlaid with a light transmission control film 620 and anopaque film 630. It is preferable that the opaque film 630 has a lighttransmissivity of 3%, the light transmission control film 620 has alight transmissivity of 20-40%, and the transparent substrate 610 has alight transmissivity of 90% or more. The light transmission control film620 and the opaque film 630 may be formed with materials havingdifferent light transmissivities, or with the same material whilebearing a thickness different from each other. For instance, in thelatter case, a chrome-based film having a thickness of 100-300 Å may beused for the light transmission control film 620, and a chrome-basedfilm sufficiently thicker than the light transmission control film 620for the opaque film 630.

According to the of light transmissivity, the mask can be divided intoA, B, C and E portions corresponding to those portions of thephotoresist film PR, and an additional F portion. The A portion has alowest light transmissivity, and the B portion has a highest lighttransmissivity. The C portion has a light transmissivity between A andB. The E portion has a light transmissivity between B and C. The Fportion has a light transmissivity between A and C. The substrate 610,the light transmission control film 620 and the opaque film 630 are allpresent at the A portion. Only the substrate 610 is present at the Bportion. The substrate 610 and the light transmission control film 620are present at the C portion. The substrate 610 and the lighttransmission control film 620 are present at the E portion, but thelight transmission control film 620 at the E portion has a plurality ofslit patterns. The substrate 610, the light transmission control film620 and the opaque film 630 are all present at the F portion, but theopaque film 630 at the F portion has a plurality of slit patterns.

The slit patterns formed at the light transmission control film 620 andthe opaque film 630 for the E and F portions have a width narrower thanthe resolution capability of the light source for the exposure such thatthe incident light diffracts and partially passes through the slit. Anypatterns capable of inducing diffraction of the light may replace theslit patterns. For instance, mosaic patterns may be used for suchpurpose.

The reason for forming the slit or mosaic patterns at the requiredportions is to reduce the amount of light applied thereto. That is, whenany metal component is present under the photoresist film to be exposedto light, the portion of the photoresist film under the metal componentis applied with an increased amount of light due to the light reflectedagainst the metal component so that the relevant portion of thephotoresist film has a relatively small thickness compared to otherportions. Furthermore, when the photoresist film is coated onto theprotruded portion with the metal component, it is planarized to beplaced on a plane with the photoresist film at other portions withoutthe metal component so that the portion of the photoresist film over themetal component has a relatively small thickness compared to otherportions. For these reasons, slit or mosaic patterns are formed at themask portions corresponding to those of the photoresist film with theunderlying metal layers to reduce the amount of light applied thereto.Alternatively, a colored photoresist film may be used for that purpose.

As shown in FIGS. 32A and 32B, when the photoresist film PR exposedthrough the third mask is developed, a photoresist pattern PR is formed.That is, the B portion of the photoresist film over the gate and datapads 24 and 64 is completely removed, whereas the C portion of thephotoresist film over the drain electrode 66 and the pixel area ispartially removed leaving a relatively small thickness. The B portion ofthe photoresist film between the pixel area and the data line 62 iscompletely removed. The remaining A portion of the photoresist film isleft with a relatively large thickness.

Thereafter, as shown in FIGS. 33A and 33B, the passivation layer 70 atthe B portion over the data pad 64 is dry-etched while exposing the datapad 64, and the passivation layer 70 and the underlying semiconductorlayer 40 and gate insulating layer 30 at the B portion over the gate pad24 are dry-etched while partially leaving the gate insulating layer 30.At this time, the gate insulating layer 30 over the gate pad 24 may becompletely removed while exposing the underlying gate pad 24. Thepassivation layer 70 and the gate insulating layer 30 at the B portionbetween the pixel area and the data line 62 are removed while partiallyleaving the gate insulating layer 30.

Thereafter, as shown in FIGS. 34A and 34B, the C portion of thephotoresist film PR over the passivation layer 70 are removed throughoxygen-based ashing.

Then, as shown in FIGS. 35A and 35B, the passivation layer 70 over thedrain electrode 66 and the pixel area, and the gate insulating layer 30remaining over the gate pad 24 is removed by using the photoresistpattern PR for a mask. At this time, the gate insulating layer 30remaining between the pixel area and the data line 62 is also removed.

As shown in FIGS. 36A and 36B, the semiconductor layer 40 at the pixelarea between the neighboring data lines 62 is removed by etching,thereby completing the semiconductor patterns 42.

Thereafter, as shown in FIGS. 37A to 37B, the remaining photoresist filmPR is removed. An ITO or IZO film is deposited onto the substrate 10,and etched through a fourth mask. Consequently, a pixel electrode 82, asupplemental gate pad 84 and a supplemental data pad 86 are formed whilecontacting the drain electrode 66, the gate pad 24, and the data pad 64,respectively. Furthermore, the section 31 is opened between the pixelelectrode 82 and the data line 62 to electrically separate them.

As is in the third preferred embodiment, the passivation layer 70 may bereplaced by a photosensitive organic layer. In this case, the separatesteps of processing a photoresist film may be eliminated.

This preferred embodiment, in addition to the advantages related to theprevious preferred embodiments, can minutely divide the lighttransmissivity of the third mask while simplifying the relevantprocessing steps. Furthermore, the possible short circuit between thepixel electrode 82 and the data line 62 can be prevented by forming theopening portion 31.

Fifth Preferred Embodiment

FIGS. 38A to 40 illustrate the steps of fabricating a TFT arraysubstrate according to a fifth preferred embodiment of the presentinvention. In this preferred embodiment, other components and structuresof the array substrate are similar to those related to the firstpreferred embodiment except that a single layered structure is used forthe gate and data line assemblies, the conductive pattern 68 for thestorage capacitor is eliminated, and a black matrix 90 and a colorfilter 100 are newly introduced.

In the method of fabricating the TFT array substrate according to thefifth preferred embodiment, the processing steps are similar to thoserelated to the first preferred embodiment prior to the step ofdepositing the ITO or IZO film to form the pixel electrode 82.

As shown in FIG. 38B, after the semiconductor layer 40 is etched to forma semiconductor pattern and the remaining photoresist film PR isremoved, an organic black matrix layer is deposited onto the substrate10, and etched through a fourth mask to form a black matrix pattern 90.Alternatively, a black photoresist film may be used to form such a blackmatrix pattern.

Then, as shown in FIG. 39, a color filter 100 of red, green and blue isformed at the pixel area between the neighboring data lines 62. Thecolor filter 100 formed through screen printing, or photolithographyusing fifth to seventh masks.

Finally, as shown in FIG. 40, an ITO film having a thickness of 400-500Å is deposited onto the substrate 10, and etched through a fifth oreighth mask. Consequently, a pixel electrode 82, a supplemental gate pad84, and a supplemental data pad 86 are completed.

In the resulting TFT array substrate, the black matrix 90 formed at thedisplay area is to prevent light leakage due to the electric fieldpresent at the periphery of the pixel electrode 82. The portion of theblack matrix 90 over the gate line 22 may be removed. The black matrix90 has a narrow contact window for exposing the drain electrode 66 thatis positioned at the center of the contact window 71 passing through thepassivation layer 70.

The color filter 100 formed on the gate insulating layer 30 between theneighboring data lines 62 is alternated with the colors of red, greenand blue. Such a color filter may be formed per one pixel area or perone longitudinal area defined by the neighboring data lines 62. Thecolor filter 100 may be extended over the contact window 71. In thiscase, the color filter 100 should also have a separate contact windowfor interconnecting the drain electrode 66 and the pixel electrode 82.Such a contact window for the color filter 100 should have a size of atleast 4 μ×4 μ because the color filter 100 is usually formed by using alarge size aligner-based light exposure.

The above-mentioned structure can simplify the steps of fabricating theTFT array substrate. Furthermore, the black matrix 90 and the colorfilter 100 formed on the TFT array substrate, the marginal error whencombining the TFT array substrate and the color filter substrate neednot be considered, and can improve the opening ratio of the device.

Sixth Preferred Embodiment

FIGS. 41A and 41B illustrate the structure of a TFT array substrateaccording to a sixth preferred embodiment of the present invention. Inthis preferred embodiment, other components and structures of the TFTarray substrate are similar to those related to the fifth preferredembodiment except that the black matrix 90 is absent. That is, among theprocessing steps for fabricating the TFT array substrate, the step offorming a black matrix pattern 90 is eliminated.

In the above structure, the opening ratio of the device is reducedcompared to that related to the fifth preferred embodiment, but theblack matrix to be formed with a common electrode at the oppositesubstrate can reduce the resistance of the common electrode.

Seventh Preferred Embodiment

FIGS. 42A to 45 illustrate the steps of fabricating a TFT arraysubstrate according to a seventh preferred embodiment of the presentinvention. In this preferred embodiment, other components and structuresof the TFT array substrate are the similar to those related to the sixthpreferred embodiment except that the passivation layer 70 has a newstructure. For such a purpose, the passivation layer 70 is formed afterthe formation of the semiconductor pattern.

As shown in FIG. 42B, a gate line assembly 22, 24 and 26 is first formedat the substrate 10 by using a first mask. A gate insulating layer, asemiconductor layer, an ohmic contact layer, and a metal data line layerare then sequentially deposited onto the substrate 10. The metal dataline layer, the ohmic contact layer and the semiconductor layer areetched through a second mask to form the desired patterns. Thesemiconductor pattern 40, the ohmic contact pattern 50, and the dataline assemblies 62 to 66 have similar shapes except that thesemiconductor pattern 40 is present at the channel region between thesource and drain electrodes 65 and 66.

A single mask 2011 is used for the second mask. The mask 200 has atransparent substrate 210 overlaid with a light transmission controlfilm 220 and an opaque film 230. As shown in FIG. 43, the portion of themask corresponding to the data line assemblies 62 to 66 is provided withthe light transmission control film 220 and the opaque film 230, and thelight transmissivity thereof is set to be 3% or less. The portion of themask corresponding to the semiconductor pattern 40 between the sourceand drain electrodes 65 and 66 is provided with the light transmissioncontrol film 220, and the light transmissivity thereof is established tobe 20 to 40%. The remaining portion of the mask is provided only withthe transparent substrate 210, and the light transmissivity thereof isestablished to be 90% or more.

In the above etching process using the second mask, a photoresist filmPR is first coated onto the substrate 10, and exposed to light throughthe second mask. The photoresist film is then developed to thereby forma photoresist pattern.

Thereafter, the metal data line layer exposed through the photoresistpattern is etched while exposing the underlying ohmic contact layer. Inthis process, either a wet-etching technique or a dry-etching techniquecan be used, preferably under the condition that only the metal dataline layer is etched while leaving the photoresist pattern. However, inthe case of the dry etching, since it is difficult to make such acondition, the photoresist pattern may be allowed to be etchedaltogether.

When the metal data line layer is formed of Cr, wet etching ispreferably used, with a solution of CeNHO₃. When the metal data linelayer is formed of Mo or MoW, dry etching is preferably used, with amixture of CF₄ and HCl or CF₄ and O₂.

As a result, the patterns 62 to 66 of the data line assembly are formedwhile exposing the underlying ohmic contact layer, except that thesource and drain electrodes 65 and 66 are not yet separated from eachother.

Thereafter, the exposed ohmic contact layer and the underlyingsemiconductor layer are removed through dry etching. Then, thephotoresist film remaining over the channel portion of the metal dataline layer between the source and drain electrode portions is removed.

The channel portion of the metal data line layer and the underlyingohmic contact layer are removed through etching. At this time, both themetal data line layer and the ohmic contact layer may be dry etched.Alternatively, dry etching the ohmic contact layer is dry etched and themetal data line layer is wet etched. In the former case, the etching ispreferably performed under the condition that the etching selectionratio with respect to the metal layer and the contact layer is high. Thereason is that when the etching selection ratio is low, it becomesdifficult to find the final etching point and the thickness of thesemiconductor pattern to be left at the channel region cannot becontrolled in an appropriate manner. In the latter case, the sideportions of the metal layer being etched with the wet etching method areetched while leaving those portions of the contact layer being etched bythe dry etching, rendering stepped portions. The mixture of CF₄ and O₂is preferably used to form the semiconductor pattern 40 with a uniformthickness.

In this way, the source electrode 65 and the drain electrode 66 areseparated from each other, completing the patterns 62 to 66 of the dataline assembly and the underlying ohmic contact pattern 50.

Thereafter, the photoresist film remaining over the data line assemblyis removed.

As shown in FIG. 44, a passivation layer 70 is deposited onto thesubstrate 10 with the data line assembly, and etched through a thirdmask to form contact windows 71 to 73. An organic black matrix layer isthen deposited onto the substrate 10, and etched through a fourth maskto form a black matrix pattern 90.

Finally, as shown in FIG. 45, a color filter 100 as well as a pixelelectrode 82, a subsidiary gate pad 84 and a subsidiary data pad 86 areformed at the substrate 10 in the similar way as in the sixth preferredembodiment.

As is in the previous preferred embodiment, the above structure ortechnique can reduce the number of the processing steps, and enhance theopening ratio of the device.

Eighth Preferred Embodiment

FIGS. 46A and 46B illustrate the structure of a TFT array substrateaccording to an eighth preferred embodiment of the present invention. Inthis preferred embodiment, other components and structures of the TFTarray substrate are the same as those related to the seventh preferredembodiment except that the passivation layer 70 is absent. The blackmatrix pattern 90 also serves the function of the passivation layer 70.The black matrix pattern 90 is extended over the peripheral portion P.As the extension of the black matrix pattern 99 over the peripheralportion P may be realized also in the seventh preferred embodiment, onlythe step of processing the passivation layer 70 is skipped in thispreferred embodiment. In this way, the number of processing steps can bereduced.

Ninth Preferred Embodiment

FIGS. 47A and 47B illustrate the structure of a TFT array substrateaccording to a ninth preferred embodiment of the present invention. Inthis preferred embodiment, other components and structures of the TFTarray substrate are similar to those related to the fifth preferredembodiment except that the passivation layer 70 is absent, and the blackmatrix 90 serves the function of the passivation layer 70. Therefore,the separate step of forming the passivation layer 70 is eliminated inthis preferred embodiment.

The black matrix 90 is formed with a photosensitive material containingblack pigments. In the etching process based on the third mask, thephotosensitive matrix layer is itself exposed to light through the thirdmask without forming the photosensitive film PR, and developed tothereby form the black matrix pattern 90. In the subsequent processingsteps, the black matrix pattern 90 serves the function of thephotoresist pattern PR.

In the above structure, the number of the processing steps can bereduced.

Tenth Preferred Embodiment

FIGS. 48A and 48B illustrate the structure of a TFT array substrateaccording to a tenth preferred embodiment of the present invention. Inthis preferred embodiment, other components and structures of the TFTarray substrate are similar to those related to the ninth preferredembodiment except that the gate insulating layer 30 has a differentpattern. That is, the portion of the gate insulating layer at the pixelarea between the neighboring data lines is removed such that it has thesame shape as that of the semiconductor pattern 40. Therefore, the colorfilter 100 is positioned directly over the substrate 10 and the gateline 22. The width of the removed portion of the gate insulating layerat the pixel area should be 1 μ or more. That is, the opening width ofthe semiconductor layer 40 should reach 1 μ or more. The openingprevents the currents from leaking between the neighboring data lines 62via the semiconductor layer 40.

In the method of fabricating the TFT array substrate according to thetenth preferred embodiment, the processing steps are similar to thoserelated to the ninth preferred embodiment except that a usual mask withonly a transparent portion and an opaque portion is used for the thirdmask. That is, the transparent portion of the mask corresponds to theportion of the target film to be removed, while the opaque portioncorresponds to the portion of the target film to remain.

When the photosensitive black matrix pattern 90 is formed by using theusual mask, and the underlying semiconductor layer and gate insulatinglayer are etched by using the photosensitive black matrix pattern 90 asa photoresist pattern PR, exposing the portions of the substrate 10 andthe gate line 21 between the neighboring data lines 62 to the outside,and the contact windows 71 to 73 are also formed.

Thereafter, a color filter 100 as well as a pixel electrode 82, asupplemental gate pad 84 and a supplemental data pad 86 are formed inthe similar way as in the ninth preferred embodiment. The color filter100 completely covers the exposed portion of the gate line 22 toinsulate the gate line 22 from the pixel electrode 82.

The above mentioned structure can reduce, the number of processing stepseven with the usual mask having only transparent and opaque portions.

As described above, the TFT array substrate of the present invention canbe fabricated with simplified processing steps while achieving goodperformance characteristics.

While the present invention has been described in detail with referenceto the preferred embodiments, those skilled in the art will appreciatethat various modifications and substitutions can be made thereto withoutdeparting from the spirit and scope of the present invention as setforth in the appended claims.

1. A thin film transistor array substrate for a liquid crystal display,comprising: an insulating substrate; a gate line assembly formed on thesubstrate, the gate line assembly having a plurality of gate linesproceeding in the horizontal direction, gate electrodes branched fromthe gate lines, and gate pads connected to end portions of the gatelines; a gate insulating layer formed on the gate line assembly, thegate insulating layer having a first contact window exposing the gatepad, and an opening portion partially exposing the insulating substrate;a semiconductor pattern formed on the gate insulating layer; a contactpattern formed on the semiconductor pattern; a data line assembly formedon the contact pattern with substantially the same outline as thecontact pattern, the data line assembly having data lines proceeding inthe vertical direction, source electrodes branched from the data lines,data pads connected to end portions of the data lines, and drainelectrodes positioned opposite to the source electrodes with respect tothe gate electrode while being separated from the source electrodes; apassivation layer formed on the data line assembly with the same outlineas the semiconductor pattern except at portions of a second contactwindow exposing the data pad and a third contact window exposing thedrain electrode; a pixel electrode formed at a pixel area defined by theneighboring gate and data lines, the pixel electrode being electricallyconnected to the drain electrode through the third contact window whilepartially contacting the gate insulating layer; and subsidiary gate anddata pads contacting the gate and data pads, respectively.
 2. The thinfilm transistor array substrate of claim 1 wherein the opening portionexposes the substrate between the pixel electrode and the neighboringdata line.
 3. The thin film transistor array substrate of claim 1wherein the third contact window exposing the drain electrode isextended such that the borderline of the drain electrode is exposed tothe outside.
 4. A thin film transistor array substrate for a liquidcrystal display comprising: an insulating substrate; a gate lineassembly formed on the substrate, the gate line assembly having aplurality of gate lines proceeding in the horizontal direction, gateelectrodes branched from the gate lines, and gate pads connected to endportions of the gate lines; a first insulating layer formed on the gateline assembly, the first insulating layer having a first contact windowexposing the gate pad; a semiconductor pattern longitudinally formed onthe first insulating layer in the vertical direction; a data lineassembly formed on the semiconductor pattern, the data line assemblyhaving data lines proceeding in the vertical direction, sourceelectrodes branched from the data lines, data pads connected to endportions of the data lines, and drain electrodes positioned opposite tothe source electrodes with respect to the gate electrodes while beingseparated from the source electrodes; a second insulating layer formedon the data line assembly with the same outline as the semiconductorpattern, the second insulating layer having a second contact windowexposing the gate pad through the first contact window, a third contactwindow exposing the data pad, and a fourth contact window exposing thedrain electrode; a color filter formed at a pixel area defined by theneighboring gate and data lines; and a pixel electrode formed on thecolor filter, the pixel electrode being connected to the drain electrodethrough the fourth contact window.
 5. The thin film transistor arraysubstrate of claim 4 further comprising a contact layer formed betweenthe semiconductor pattern and the data line assembly with the sameoutline as the data line assembly.
 6. The thin film transistor arraysubstrate of claim 4 further comprising supplemental gate pads andsupplemental data pads covering the gate pad and the data pad,respectively.
 7. The thin film transistor array substrate of claim 4further comprising a photo-interceptive organic pattern formed betweenthe data line assembly and the overlying passivation layer.
 8. The thinfilm transistor array substrate of claim 7 wherein thephoto-interceptive pattern is provided with a fifth contact windowexposing the drain electrode through the fourth contact window, thefifth contact window being narrower than the fourth contact window. 9.The thin film transistor array substrate of claim 4 wherein the secondinsulating layer is formed of a photo-interceptive organic layer. 10.The thin film transistor array substrate of claim 9 wherein the firstinsulating layer has the same outline as the semiconductor pattern. 11.The thin film transistor array substrate of claim 10 wherein the openingwidth of the semiconductor pattern between the neighboring data lines is1 μ or more.
 12. A thin film transistor array substrate for a liquidcrystal display, comprising: an insulating substrate; a gate lineassembly formed on the substrate, the gate line assembly having aplurality of gate lines proceeding in the horizontal direction, gateelectrodes branched from the gate lines, and gate pads connected to endportions of the gate lines; a first insulating layer formed on the gateline assembly, the first insulating layer having a first contact windowexposing the gate pad; a semiconductor pattern longitudinally formed onthe first insulating layer in the vertical direction; a data lineassembly formed on the semiconductor pattern, the data line assemblyhaving data lines proceeding in the vertical direction, sourceelectrodes branched from the data lines, data pads connected to endportions of the data lines, and drain electrodes positioned opposite tothe source electrodes with respect to the gate electrodes while beingseparated from the source electrodes, the data line assemblysubstantially having the same outline as the semiconductor patternexcept the portion placed between the source electrode and the drainelectrode; a second insulating layer formed on the data line assembly,the second insulating layer having a second contact window exposing thefirst contact window, a third contact window exposing the data pad, anda fourth contact window exposing the drain electrode; a color filterformed on the passivation layer at a pixel area defined by theneighboring gate and data lines; and a pixel electrode formed on thecolor filter, the pixel electrode being connected to the drain electrodethrough the fourth contact window.
 13. The thin film transistor arraysubstrate of claim 12 further comprising a contact layer formed betweenthe semiconductor pattern and the data line assembly substantially withthe same outline as the data line assembly.
 14. The thin film transistorarray substrate of claim 12 further comprising supplemental gate padsand supplemental data pads covering the gate pads and the data pads,respectively.
 15. The thin film transistor array substrate of claim 12further comprising a photo-interceptive organic pattern formed on thepassivation layer over the data line assembly and the gate lineassembly.
 16. The thin film transistor array substrate of claim 15wherein the photo-interceptive organic pattern is provided with a fifthcontact window exposing the drain electrode through the fourth contactwindow, the fifth contact window being narrower than the fourth contactwindow.
 17. The thin film transistor array substrate of claim 12 whereinthe second insulating layer is formed with a photo-interceptive organiclayer.
 18. A thin film transistor array substrate for a liquid crystaldisplay comprising: an insulating substrate; a gate line assembly formedon the substrate, the gate line assembly having a plurality of gatelines proceeding in the horizontal direction, gate electrodes connectedto the gate lines, and gate pads connected to end portions of the gatelines; a first insulating layer formed on the gate line assembly, thefirst insulating layer having a first contact window exposing the gatepad, and an opening portion partially exposing the insulating substrate;a semiconductor pattern formed on the first insulating layer; a contactpattern formed on the semiconductor pattern; a data line assembly formedon the contact pattern with substantially the same outline as thecontact pattern, the data line assembly having data lines proceeding inthe vertical direction, source electrodes connected to the data lines,data pads connected to end portions of the data lines, and drainelectrodes positioned opposite to the source electrodes with respect tothe gate electrode while being separated from the source electrodes; asecond insulating layer formed on the data line assembly with the sameoutline as the semiconductor pattern except at portions of a secondcontact window exposing the data pad and a third contact window exposingthe drain electrode; a pixel electrode formed at a pixel area defined bythe neighboring gate and data lines, the pixel electrode beingelectrically connected to the drain electrode through the third contactwindow while partially contacting the first insulating layer; andsubsidiary gate and data pads contacting the gate and data pads,respectively.
 19. The thin film transistor array substrate of claim 18,wherein the third contact window exposing the drain electrode isextended such that the borderline of the drain electrode is exposed tothe outside.
 20. The thin film transistor array substrate of claim 18,wherein the second insulating layer is the photo-interceptive layer. 21.The thin film transistor array substrate of claim 18, wherein the dataline assembly has a double layered structure comprising a first metalliclayer and a second metallic layer, and the first metallic layer isformed of at least one of a material such as Cr, Mo or Mo alloy, and thesecond metallic layer is formed of at least one of a material such as Alor Al alloy, and the pixel electrode is electrically connected to thefirst metallic layer.